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XE1205
Name
Ptol(1:0)
Bits
1-0
Address
10
RW
r/w
Description
Number of tolerated errors for the pattern recognition:
00 -> 0 error
01 -> 1 error
10 -> 2 errors
11 -> 3 errors
FEI_out(15:8)
FEI_out(7:0)
7-0
7-0
11
12
r
r
FEI output
in a 2’s complement representation
Table 20: RXParam configuration register
7.2.6
Pattern register
1 byte of the reference pattern
Name
Reg_pattern(31:24)
Reg_pattern(23:16)
Reg_pattern(15:8)
Reg_pattern(7:0)
Bits
7-0
7-0
7-0
7-0
Address
13
14
15
16
RW
r/w
Description
st
2 nd byte of the reference pattern
3 rd byte of the reference pattern
4 th byte of the reference pattern
Table 21: Pattern register
This register holds the user supplied reference pattern of 8, 16, 24, or 32 bits (see the RXParam_Psize(1:0) parameter).
The first byte of this pattern is always stored in the byte at address 13. If used, the 2 nd byte is stored at address 14, the
3 rd byte at address 15 and finally the 4 th byte at 16. The MSB bit of the reference pattern is always bit 7 of address 13.
Comparing the demodulated data, the first bit received is compared with bit 7 (the MSB) of byte address 13. The last bit
received is compared with bit 0 (the LSB) in the Pattern register.
Table 22 provides an example of pattern recognition with a 32-bit pattern.
Byte Address
13
Bit 7 Bit 0
10010011
101 10010011
Byte Address
14
Bit 7 Bit 0
10101010
10101010
previous bits from
Byte Address
15
Bit 7 Bit 0
10010011
10010011
Byte Address
16
Bit 7 Bit 0
10101010
10101010
last bit received
demodulator
Table 22: Pattern recognition example (32 bits)
Table 23 provides an example of pattern recognition with an 8-bit pattern.
Byte Address
13
Bit 7 Bit 0
10010011
Byte Address
14
Bit 7 Bit 0
Xxxxxxxx
Byte Address
15
Bit 7 Bit 0
Xxxxxxxx
Byte Address
16
Bit 7 Bit 0
Xxxxxxxx
101 10010011
previous bits from
last bit received
demodulator
Table 23: Pattern recognition example (8 bits)
? Semtech 2008
33
www.semtech.com
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